Date: Friday, August 2, 2013
Time: 11:00 am
Speaker: Prof. Lian-Mao Peng, Peking University
Title: Carbon Nanotube Electronics: Extending the Moore Law to the End of the Roadmap and Beyond
Location: 67-3111 Chemla room
Hosted by: Gary Ren
Carbon nanotubes (CNT) are quasi-one-dimensional materials with unique properties and are ideal material for nanoelectronics. In particular, perfect n-type [1-2] and p-type  contacts are now available for controlled injection of electrons into the conduction band and holes into the valence band of the CNT, paving the way for a doping free fabrication of CNT based ballistic CMOS , high performance optoelectronic devices [5-6], and integrated circuits [7,8]. The feasibility of this doping free CMOS technology has been demonstrated by fabricating CMOS circuits, including a full adder circuit, on a SiO2/Si substrate, demonstrating perfect symmetric device characteristics for the n-type and p-type CNT FETs based on the same single walled CNT. This CNT based CMOS technology only requires the patterning of arrays of parallel semiconducting CNTs with moderately narrow diameter range, e.g. 1.6-2.4nm, instead of the more stringent chirality control on the CNT. This may lead to the integration of CNT based CMOS devices or entire carbon based circuit with increasing complexity and possibly find its way into logic and optoelectronic circuits. The development of high performance CMOS circuits also requires high quality gate dielectric with high dielectric constant. Although various high-κ dielectrics have been demonstrated to be technically compatible with carbon-based devices, it is proved to be very difficult to grow uniform thin high-κ film directly on the surface of CNTs or graphene via a general method, for example, atomic layer deposition (ALD). Utilizing the excellent wetting behavior of yttrium on sp2 carbon framework , ultrathin (about few nm) and uniform Y2O3 layers have been directly grown on the surfaces of CNT and graphene without using noncovalent functionalization layers or introducing large structural distortion and damage. A top-gate CNT FET adopting this top-gate dielectric shows excellent device characteristics, including an ideal subthreshold swing of 60 mV/decade. The high electrical quality Y2O3 dielectric layer has also been integrated into a graphene FET as its top-gate dielectric with a capacitance of up to 1200 nF/cm2, showing an improvement on the gate efficiency and on state transconductance of over 100 times when compared with that of its back-gate counterpart [9-10].