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Date: Tuesday, February 24, 2015
Time: 11:00 am
Speaker: Michael A. Guillorn, IBM T. J. Watson Research Center
Title: Self-assembled, self-aligned and self healing: CMOS scaling enabled by stochastic suppression at the nanoscale
Location: 67-3111 Chemla Room


The end of CMOS density scaling has been erroneously predicted by a number of authors for several decades. A review of some of this work was presented by Haensch, et al[1]. Many of these predictions arose from a belief that the only possible solutions to the challenges presented by device and circuit scaling would result from linear extrapolations of existing technology. In reality, the incorporation of new materials, device structures and patterning techniques has consistently prolonged the “life” of Si-based CMOS. As CMOS technology enters the era of single digit process nodes, a more fundamental limitation has manifested itself: stochastic variation. In 65 nm node technology, the budget for CD uniformity, line edge roughness (LER), line width roughness (LWR) and overlay exceeded 10 nm. At the 10 nm process node, all of these values are on the order of a few nanometers with several critical feature sizes expected to be below 10 nm. This raises an important question: how do we continue scaling when variation tolerances approach 1 nm?

In this paper we will present results from device and patterning research that illuminate some of the limitations to CMOS device and circuit fabrication arising from stochastic variation. In particular, performance degradation arising from poor CD uniformity, LER and LWR in scaled FinFET devices will be reviewed. We will discuss the advantages of the gate-all-around device architecture as a variation tolerant device structure relative to scaled FinFET structures. Our work on techniques for suppressing variation at the nanoscale by using self-healing anneals will be presented demonstrating device channels with less than 1 nm of CD nonuniformity, LER and LWR [2]. Methods for patterning these structures using block copolymer directed self-assembly (DSA) will also be discussed [3]. Techniques for forming high-density circuit patterns using these processes will be presented with an emphasis on the introduction of self-aligned pattern formation techniques. These combined results show a path for continued CMOS density scaling without performance loss.